Fpga Embedded Design, Part 4 - Microprocessor Design
Last updated 1/2022
Created by Eduardo Corpeño, Marissa Siliezar
MP4 | Video: h264, 1920x1080 | Audio: AAC, 44.1 KHz, 2 Ch
Level: Intermediate | Genre: eLearning | Language: English + subtitle | Duration: 129 Lectures ( 5h 26m ) | Size: 1.6 GB
✓ How a CPU works.
✓ How to design a CPU core of your own.
✓ How to design an Instruction Set Architecture
✓ How to design a CPU core in Verilog.
✓ How to synthesize a CPU core for Altera and Xilinx FPGAs.
Requirements
● The Verilog Hardware Description Language.
● FPGA Design.
● Knowledge of any Electronic Design Automation Tool for FPGAs.
Description
It's time to take on a Challenge! How does designing a CPU sound?
In this fourth part of the FPGA Embedded Design series, we'll design a CPU from scratch to finally get it up and running on several platforms.
We'll write most of the code in the Vivado Design Suite, but you'll have the chance to see it working as well in Quartus Prime, EDA Playground or LabsLand, so you can follow along with your favorite tools. The FPGA boards we'll use are the BASYS3, by Digilent (with a Xilinx FPGA), and the DE0-CV from Terasic (with an Intel FPGA).
This course consists of three main parts
• Foundations of Computer Architecture, where we'll cover the essentials of CPU design and jargon.
• Design of our own CPU, where we'll make several design decisions to come up with a soft processor that meets our needs.
• Hands-On Development, where we'll write the code, simulate and finally get our CPU into an FPGA board. No purchases are required for this part, but it sure helps to have your own board to follow along, and keep on tinkering in the future with your new soft processor.
What are you waiting for? Let's have fun designing a CPU!!!
Who this course is for
■ Embedded designers who want to dive deeper into Soft-Processor design.
■ Intermediate FPGA enthusiasts who are curious about CPU design.
■ Anyone are taking the FPGA Embedded Design series by Closure Labs.
Fpga Embedded Design, Part 4 - Microprocessor Design
